For example, a technology where after an extension layer of an nMOS transistor is formed in a low voltage nMOS region, an offset spacer is formed in side surfaces of a gate electrode, and after that, an extension layer of a pMOS transistor is formed in a low voltage pMOS region is disclosed in Japanese Patent Application Laid-Open Publication No. 2003-100902 (Patent Document 1).
In addition, a semiconductor device that includes a gate electrode formed on a semiconductor layer of an SOI substrate via a gate insulation film, a side wall spacer formed on side walls of the gate electrode, a semiconductor layer for a source-drain that is made to be grown epitaxially on a semiconductor layer, and a sidewall spacer formed on side walls of the semiconductor layer for the source-drain is disclosed in Japanese Patent Application Laid-Open Publication No. 2014-038878 (Patent Document 2).